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A typical controller interface for the BP7B is shown in figure 4. An on signal (IPM control input low) is
generated by pulling the respective control input low (GND) using a CMOS buffer capable of sinking at least
16mA (74HC04 or similar). In the off state the buffer should actively pull the control input high to maintain good
noise immunity. Open collector drive that allows the control input to float will degrade common mode noise
immunity and is therefore not recommended.
If the IPM’s built in protection is activated it will immediately shut down the gate drive to the affected IGBT
and pull the associated FO pin low. This causes the VLA606 to pull the fault feedback signal (Pin 9 of J2) low.
When a fault is detected by the IPM a fault signal with a minimum duration of 1ms is produced. Any signal on
the fault line that is significantly shorter than 1ms can not be a legitimate fault and should be ignored by the
controller. Therefore, for a robust noise immune design, it is recommended that an RC filter with a time constant
of approximately 10us be added to the fault feedback as shown in figure 4. An active fault signal indicates that
severe conditions have caused the IPM’s self protection to operate. The fault feedback signal should be used by
the system controller to stop the operation of the circuit until the cause of the fault is identified and corrected.
Repetitive fault operations may result in damage to the IPM.
Printed Circuit Layout:
Figure 5 shows the printed circuit layout of the BP7B interface circuit. The compact 63mm x 102mm
circuit board with only 23 components provides a complete isolated seven channel driving circuit with short
circuit, over temperature and under voltage protection. This clearly demonstrates the advantage of using L-
Series Intelligent Power Modules. One important feature of this PCB is the use of separate shield plane islands
for each of the isolated driving circuits, logic level interface, and control power supply. Four of the islands are
tied to the common of the IPM’s isolated control power supplies (pins 1, 5, 9 and 13 of J3). The remaining two
islands are connected at the logic ground (pin 10 of J2) and 24 VDC power supply ground (pin 2 of J1)
respectively. This layout is designed to prevent undesirable coupling of noise between the control side and the
floating gate drive channels. The BP7B PCB is designed to plug directly onto the control pins of the L-Series
IPM. This configuration helps to maintain good noise immunity by providing minimal interconnection distance.
More Information:
For more information refer to the following documents available from the Powerex website:
(1) L-Series IPM individual data sheets provide the detailed electrical characteristics of L-Series IPMs
(2) Application Note – “General Considerations: IGBT & IPM modules”, Provides detailed information on power
circuit design including bus bars, snubber circuits, and loss calculations. This document also includes heatsink
mechanical requirements and proper mounting procedures.
(3) Application Note – “Introduction to IPMs (Intelligent Power Modules)”, Provides detailed information regarding
features, operational characteristics, and interface circuit requirements for Intelligent Power Modules.
(4) BP6A technical data – provides interface circuit information for L-Series IPMs in the large “D” package.
(5) VLA106-24151 and VLA106-24154 individual data sheets provide detailed electrical characteristics for these
DC to DC converters.
(6) Melcosim loss simulation software - provides quick power loss estimation for L-Series IPMs in three phase
inverter applications.
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